1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device which holds data stored in a memory cell even if power is turned OFF and more particularly to the nonvolatile semiconductor memory device such as a flash EEPROM.
2. Description of the Related Art
A nonvolatile semiconductor memory device in an example shown in FIG. 3 includes: memory cells 1.sub.m (m=1, 2, . . . , M); selecting cells 2.sub.1m and 2.sub.2m ; a word line 3; first and second column lines 4.sub.1 and 4.sub.2 ; a word line drive circuit 5; column selecting circuits 6.sub.1 and 6.sub.2 ; a reading-out circuit 7; an inverter 8; a read-out drive section 9.sub.m ; a reference section 10; a sense-amplifier 11.sub.m ; and a data bus 12. Note here that this example is a circuit related to reading out data and a circuit related to data write-in and erasure is not shown.
The memory cell 1.sub.m includes a MOS transistor which has a usual gate (control gate) and also a floating gate electrically insulated from a surrounding in such a configuration that each control gate is connected through the word line 3 and also, through the word line 3, connected to an output terminal of the word line drive circuit 5. In each memory cell 1.sub.m, when a sufficiently higher voltage (10-20V) than that applied to a drain is applied to the control gate, electrons are stored from the drain into the floating gate (write-in operation) and, when polarity of the voltage applied to the control gate is changed, those electrons stored in the floating gate are moved to the drain (erasure operation). Therefore, in a case where no electrons are stored in the floating gate of each memory cell 1.sub.m, when a command for reading out data is supplied from outside to permit the word-line drive circuit 5 to apply an "H" level signal to the word line 3, the "H" level signal is applied to the control gate, thus turning ON the memory cell 1.sub.m. In a case where electrons are stored in the floating gate, on an other hand, even when the "H" level signal is applied from the word-line drive circuit 5 to the word line 3 to apply the "H" level signal to the control gate, a negative charge of the electrons stored in the floating gate inhibits a channel from being induced, so that the memory cell 1.sub.m is not turned ON and stays in an OFF-state, thus raising a threshold voltage VT. These ON-states and OFF-states correspond to one-bit states of "0" and "1" respectively.
The selecting cells 2.sub.1m each consist of a MOS transistor and are connected to one another at their gate through the first column line 4.sub.1 and also, therethrough, to an output terminal of the column selecting circuit 6.sub.1. The column selecting circuit 6.sub.1, when the first column line 4.sub.1 is selected as a result of a first-stage decoding of addresses supplied from outside, applies an "H" level signal to that first column line 4.sub.1. With this, the selecting cell 2.sub.1m is supplied with the "H" level signal at its gate and so turned ON, to form a path through which data is read out from the memory cell 1.sub.m.
The selecting cells 2.sub.2m each consist of a MOS transistor and are connected at their gate to one another through the second column line 4.sub.2 and also, therethrough, to an output terminal of the column selecting circuit 6.sub.2. The column selecting circuit 6.sub.2, when that second column line 4.sub.2 is selected as a result of a second-stage decoding of addresses supplied from the outside, applies an "H" level signal to that second column line 4.sub.2. With this, the selecting cell 2.sub.2m is supplied with the "H" level signal and so turned ON, to form a path through which data is read out from the memory cell 1.sub.m.
The reading-out circuit 7, when supplied with a data-read-out command from the outside, supplies an "H" level signal which indicates a start of a data read-out operation, to the inverter 8, the read-out driving circuit section 9.sub.m, and the reference section 10. The inverter 8 inverts the "H" level signal supplied from the reading-out circuit 7 into an "L" level signal and then supplies it to the read-out driving section 9, and the reference section 10.
The read-out driving section 9.sub.m roughly includes a driving transistor 13.sub.m, a path forming transistor 14.sub.m, a path cutting-off transistor 15.sub.m, and a NOR gate 16.sub.m.
The driving transistor 13.sub.m consists of a MOS transistor and is turned ON by an "H" level signal supplied from the reading-out circuit 7 in order to apply a voltage V, which corresponds to an ON-state or OFF-state of the memory cell 1.sub.m, to a first input terminal of the sense-amplifier 11.sub.m. The path forming transistor 14.sub.m consists of a MOS transistor and is turned ON by an "H" level signal supplied from the NOR gate 16.sub.m. in order to form a path for reading out data from the memory cell 1.sub.m. The path cutting-off transistor 15, consists of a MOS transistor and is turned ON by an "H" level signal supplied from the inverter 8 in order to cut off a path for reading out data from the memory cell 1.sub.m. The NOR gate 16.sub.m, which has its first input terminal supplied with an output signal of the inverter 8 and its second input terminal connected with a source of the path forming transistor 14.sub.m, outputs an "H" level signal to turn ON the path forming transistor 14. when both the output signal of the inverter 8 and the source voltage of the path forming transistor 14.sub.m are of an "L" level.
The reference section 10 roughly includes a reference cell 21, selecting cells 22.sub.1 and 22.sub.2, a word-line driving circuit 23, column selecting circuits 24.sub.1 and 24.sub.2, a driving transistor 25, a path forming transistor 26, a path cutting-off transistor 27, and a NOR gate 28.
The reference cell 21 consists of a MOS transistor having a same construction and characteristics as the memory cell 1.sub.m and is set beforehand in such a state that no electrons are stored in its floating gate, an ON-state. The selecting cell 22.sub.1, the selecting cell 22.sub.2, the word-line driving circuit 23, the column selecting circuit 24.sub.1, the column selecting circuit 24.sub.2, the path forming transistor 26, the path cutting-out transistor 27, and the NOR gate 28 have a same construction and characteristics as the selecting cell 21.sub.m, the selecting cell 22.sub.m, the word-line driving circuit 5, the column selecting circuit 6.sub.1, the column selecting circuit 6.sub.2, the path forming transistor 14.sub.m, the path cutting-off transistor 14.sub.m, the path cutting-out transistor 15.sub.m, and the NOR gate 16.sub.m. respectively. This is so set that the sense-amplifier 11.sub.m, including a differential amplifier, may have its first and second input terminals respectively connected with two loads equal as much as possible.
Since the read-out driving section 9.sub.m is provided one for each memory cell 1.sub.m and, on the other hand, the reference section 10 is provided one for M number of the sense-amplifiers 11.sub.m, the driving transistor 25 generally has two to three times the size of the driving transistor 13.sub.m in order to acquire a current driving capability. The driving transistor 25, when turned ON by an "H" level signal supplied from the reading-out circuit 7, applies a voltage V.sub.R which corresponds to the ON-state of the reference cell 21, to the second input terminal of the sense-amplifier 11.sub.m.
The sense-amplifier 11.sub.m, as mentioned above, includes a differential amplifier, so that it detects and amplifies a difference between a voltage supplied from the read-out driving section 9.sub.m and a voltage V.sub.R supplied from the reference section 10 and then outputs data via the data bus to the outside.
Steady characteristics of such prior-art nonvolatile semiconductor memory device are represented by a curve a for the voltage vs. current characteristic of the driving transistor 13.sub.m and a curve b for the voltage vs. current characteristics of the driving transistor 25.sub.m as shown in FIG. 4. That is, the driving transistors 13.sub.m and 25 have different current driving capabilities because of their different sizes, hence different gradients in their characteristics curves. The reason is described as follows.
In the case where no electrons are stored in the floating gate of the memory cell 1.sub.m, when an "H" level signal is applied to the control gate of the memory cell 1.sub.m with the driving transistor 13.sub.m, the path forming transistor 14.sub.m, and the selecting cells 21.sub.m and 2.sub.2m held in the ON-state, the memory cell lm is turned ON, so that a voltage V.sub.DM applied by the driving transistor 13.sub.m to the first input terminal of the sense-amplifier 11.sub.m drops in voltage from a power-supply voltage V.sub.CC by a voltage value corresponding to a total of the turn ON resistances of the path forming transistor 14, the selecting cells 21.sub.m and 2.sub.2m, and the memory cell 1.sub.m, down to a voltage V.sub.Don, thereby flowing a current I.sub.on through the driving transistor 13.sub.m as indicated by a point A in FIG. 4.
In the case where electrons are stored in the floating gate of the memory cell 1.sub.m, on the other hand, even when an "H" level signal is applied with the driving transistor 13.sub.m, the path forming transistor 14.sub.m, and the selecting cells 2.sub.1m and 2.sub.2m held in the ON-state, the memory cell still stays in the OFF-state, so that the voltage V.sub.DM applied by the driving transistor 13.sub.m to the first input terminal of the sense-amplifier 11 becomes roughly equal to the power-supply voltage V.sub.CC, thereby permitting little current to flow through the driving transistor 13.sub.m as indicated by a point B in FIG. 4.
Thus, when the memory cell 1.sub.m is in the ON-state, the voltage V.sub.DM becomes the voltage V.sub.Don and, when it is in the OFF-state, the voltage V.sub.DM roughly becomes the power-supply voltage V.sub.CC ; with this, in order that the sense-amplifier 11.sub.m can detect whether the memory cell 1.sub.m is in the ON-state or the OFF-state, the driving transistor 25 is sized to have such voltage vs. current characteristics that the voltage V.sub.R applied to the second input terminal of the sense-amplifier 11.sub.m by the driving transistor 25 when the reference cell 21 is in the ON-state may be approximately at the middle between the voltage V.sub.Don and the power-supply voltage V.sub.CC (see a point C in FIG. 4).
In the above-mentioned prior-art nonvolatile semiconductor memory device, however, when the path forming transistor 14.sub.m and the selecting cells 2.sub.1m and 2.sub.2m are turned ON, the memory cell 11 is directly connected to the first input terminal of the sense-amplifier 11.sub.m, so that when the memory cell 1.sub.m is in the ON-state, the memory cell 1.sub.m itself acts to pull the voltage V.sub.DM applied to the first input terminal of the sense-amplifier 11.sub.m from the power-supply voltage V.sub.CC down to the voltage V.sub.Don.
With increasing integration densities and fine patterning degrees of nonvolatile semiconductor memory devices in recent years, a current flowing through the memory cell 1.sub.m has been more and more reduced to a very small value of 10-20 .mu.A, so that it takes rather a long time for the memory cell 1.sub.m to be pulled in voltage from V.sub.DM down to V.sub.Don, thus delaying the time for reading out data.
In the above-mentioned prior-art nonvolatile semiconductor memory cell, moreover, one reference section 10 drives M number of sense-amplifiers 11.sub.m, so that the driving transistor 25 must be sized two to three times as large as the driving transistor 13.sub.m, which leads to a following problem.
That is, when the device starts to read out data, both the voltages V.sub.DM and V.sub.R applied to the first and second input terminals respectively of the sense-amplifier urn rise in level along almost the same course as shown in FIG. 5 until the selecting cells 2.sub.1m and 2.sub.2m and the selecting cells 22.sub.1 and 22.sub.2 are turned ON (all of which are done so almost simultaneously), up to a time t.sub.1.
However, as mentioned above, the driving transistor 25 is large in size and so has a large current driving capability, so that immediately after the selecting cells 2.sub.1m and 2.sub.2m and the selecting cells 22.sub.1 and 22.sub.2 are turned ON, the voltage V.sub.R starts rising more steeply than the voltage V.sub.DM as shown by a curve c.
When an "H" level signal is applied to the word line 3 afterward (time t.sub.2), the voltage V.sub.R keeps on rising at a same gradient up to a timet.sub.2 and then is saturated because the word-line driving circuit 23 is a dummy. The voltage V.sub.DM, on the other hand, lowers to some extent (see a curve a in FIG. 5) because the memory cell 1.sub.m is turned ON when no electrons are stored in the floating gate of the memory cell 1.sub.m and, when electrons are stored in the floating gate of the memory cell 1.sub.m, rises further (see a broken-line curve b in FIG. 5) because the memory cell lm stays OFF.
Therefore, until a time t.sub.3 comes, it cannot accurately be decided whether the voltage V.sub.DM is larger or smaller than the voltage V.sub.R ; that is, from the time t.sub.2 up to the time t.sub.3, data cannot be supplied to the data bus, thus taking rather long read-out time.
In the above-mentioned prior-art nonvolatile semiconductor memory device, further, although the sense-amplifier 11.sub.m is a differential amplifier, only one of its two differential inputs is given a heavy load, so that unbalance such as occurrence of an offset voltage is liable to occur. Therefore, if unbalance exists between the two input terminals of the sense-amplifier 11.sub.m, there is obtained no margin based on which the ON/OFF-state is decided of the memory cell 1.sub.m, so that the data cannot accurately be detected or amplified. One measure for preventing the occurrence of such unbalance may be to reduce the value of the number M of the sense-amplifiers 11.sub.m, which, however, would suppress an enhancement in integration density of the nonvolatile semiconductor memory device.
In the above-mentioned prior-art nonvolatile semiconductor memory device, even further, a sufficient margin to detect the OFF-state of the memory cell 1.sub.m can be obtained only if little current flows through the driving transistor 13.sub.m even when it is turned ON with the memory cell lm held in the OFF-state, so that a sufficient amount of electrons need to be stored in the floating gate of the memory cell 1.sub.m in order to write in data. It takes, however, rather long time to store electrons sufficiently in the floating gate, which may lead to the prolonged write-in time.